1. Technical Field to which the Invention Belongs
The present invention relates to a clock shaping device used as an oscillator for network synchronization, and more particularly to a clock shaping device capable of securing synchronization for a certain period even during a free-run, by switching among a reception clock signal with jitter, a back-up clock signal in sync with a clock signal distributed from a master station, and a quartz crystal oscillation circuit held therein.
2. Prior Art
The role of a clock signal in a network is to distribute a common frequency throughout the network to provide synchronization in the network. A range within which the frequency is distributed depends on the basic configuration of the network, and a network of a network synchronization type is constructed in the case of a long distance communications system. In the network of the network synchronization type, a single master station or quasi-master station distributes a clock signal at the reference frequency (hereinafter, referred to as the reference clock signal), and the reference clock signal is played back in every node within the network so as to be distributed within all the nodes. In this system, all the circuits within the network operate according to the clocks having the same frequency accuracy, which enables transmission/reception processing, such as multiplexing/separation of data, and insertion/extraction of information with the use of a memory, to be performed quite easily.
FIG. 7 is a view schematically showing the configuration of a digital network of a master-slave synchronization system, which is one type of the network synchronization. A reference clock signal for synchronization, having the frequency of f0, is distributed from a master station M to a station A and a station B used as slave stations. As is shown in FIG. 7, transmission/reception processing is normally performed in transmission portions A and B and reception portions A and B, according to a reception clock signal which is timing-extracted from reception data from the transmission path in timing-extracting portions A and B in the transmission apparatus installed in the respective slave stations.
For example, when line trouble occurs in a repeater 1 in a downlink from the slave station A to the slave station B and data cannot be transmitted properly, the slave station B is not able to receive the reception data normally, which makes it impossible to play back the reception clock signal in the timing-extracting portion B in the transmission apparatus B installed in the slave station B. This gives rise to the pulling out of synchronization in the slave station B, and the reception clock signal is switched to a back-up clock signal f0 in a clock supply apparatus B, which is in sync with the reference clock signal distributed from the master station M. The transmission/reception processing is performed according to this back-up clock signal f0 in the transmission apparatus B, which continues until the trouble in the repeater 1 on the transmission path is eliminated. When the trouble is spread and the reception clock signal extracted from the reception data from the repeater 1 is detected as being normal, the back-up clock signal is switched to the reception clock signal.
FIG. 8 is a block diagram showing the configuration of a conventional clock shaping device used in the transmission apparatus or the like forming the master-slave synchronized communications system. The clock shaping device is generally referred to as a jitter lowering circuit, and adopts the configuration that uses a PLL circuit having a voltage controlled oscillation circuit VCO or the like. In order to improve the phase noise and the jitter characteristic, as is shown in FIG. 8, some types of the clock shaping device use a voltage controlled quartz crystal oscillator VCXO or a voltage controlled SAW oscillator (VCSO) using a SAW (Surface Acoustic Wave) resonator instead of the voltage controlled oscillator VCO.
Into an input terminal FIN of the clock shaping device shown in FIG. 8 is inputted either of the clock signals (the reception clock signal in a normal state) selected in an unillustrated selection portion that switches between the reception clock signal and the back-up clock signal. A phase comparison portion 11 compares the phases between the clock signal thus inputted and a clock signal from a voltage controlled SAW oscillator (VCSO) 13a. The resulting phase difference signal is outputted to a loop filter 12, so that it is used as a control voltage Vc for frequency control in the voltage controlled SAW oscillator (VCSO) 13a. In this instance, when an omission of several clocks is detected in the clock signal inputted into the phase comparison portion 11, this information is outputted to the outside from an output terminal ALM in the form of an alarm signal, which is one of the factors to switch the clock signals to be inputted into the clock shaping device.
A communications device represented by an electronic instrument in recent years has achieved significant speed-ups as its communication speed is shifted to a GHz band. Hence, the oscillator or the clock shaping device used in the communications device has to meet the following: (1) the frequency stability is high in a high frequency band; (2) temperature compensation is ensured in a operating temperature range of the communications device; and further (3) jitter in the clock signal outputted from the oscillation circuit or the like is lowered markedly.
In addition, as the transmission apparatus or the like used in the network synchronization system described above reduces the size and the cost, there has been a strong need for a smaller, low-cost component, including the clock shaping device, used in the transmission apparatus or the like.
Incidentally, JP-A-8-274633 (Paragraph [0022], FIG. 1) and JP-A-9-307432 (Paragraph [0019], FIG. 1) have disclosed prior arts related to a PLL circuit that receives inputs of two clock signals used as the reference and generates a clock signal in sync with the either clock signal selected therefrom. JP-A-8-274633 (Paragraph [0022], FIG. 1) aims to improve the response characteristic when the reference clock signals are switched by an input detection circuit. JP-A-9-307432 (Paragraph [0019], FIG. 1) aims to improve the phase deviation of an output clock that depends on a phase difference between the two reference clock signals when the reference clock signals are switched by a selection control portion.
The system and the clock shaping device described above have problems (issues) such as the following.
There is an issue such that, when the reception clock signal is switched to the back-up clock signal in the event of an error in the reception clock signal, a time lag is generated due to a delay of an operation in the control system or an operation in the functional block, such as the switching switch forming the selection portion or the like, and the delay time thus generated delays the synchronous compensation with respect to the trouble.
Also, in the event of trouble in the reception clock signal or the back-up clock signal, the conventional clock shaping device can do nothing but outputs an omission in the back-up clock signal in the form of an alarm, and there is an issue that the clock shaping device cannot activate synchronous compensating means until the trouble or the like is spread.
In addition, there is an issue that a clock signal is outputted without any compensation for the frequency accuracy in a free-run state when neither the reception clock signal nor the back-up clock signal is inputted into the clock shaping device.
Further, in the PLL circuit configuration used in the conventional clock shaping device, it takes some time to detect an omission in the clock signal being inputted and output the detection to the outside in the form of an alarm signal due to the time needed as a lock-up time, and there is an issue that the synchronous compensation is delayed.
Also, as is shown in FIG. 9, some types of the conventional clock shaping device use an output of the voltage controlled quartz crystal oscillator VCO or the voltage controlled SAW oscillator VCSO as an output of the clock shaping device and also as a feedback loop output of the PLL circuit.
However, it is not easy to achieve matching, such as impedance matching, in an input/output interface and a transmission path (in this case, a wiring line path for connection) in a high frequency range at several hundred MHz or higher, during the delivery of the clock signal in these configurations. Hence, there is an issue that the level of the output amplitude is lowered due to mutual influence, and an issue that unbalance or a phase difference is generated in the output amplitude between the positive and negative outputs in the case of a differential output, which causes jitter to be generated.
In order to avoid such influence, as is shown in FIG. 10, an output buffer driver IC (a buffer 14b in the drawing) fabricated in the form of an integrated circuit (hereinafter, abbreviated to IC) is inserted separately in each output portion of the voltage controlled quartz crystal oscillation circuit or the voltage controlled SAW oscillation circuit. In this case, there is an issue that the number of components is increased by adding the output buffer driver IC, which makes a reduction in size and cost difficult.
The invention was devised to eliminate the issues described above, and therefore has an object to provide a clock shaping device capable of performing synchronous compensation early in a case where synchronization is lost due to trouble in the reception clock signal or the back-up clock signal. Also, the invention has an object to provide a clock shaping device capable of performing synchronous compensation with the use of a quartz crystal oscillation circuit held in the clock shaping device even when these clock signals are not supplied. In addition, the invention has an object to achieve a clock shaping device that does not give direct influence to the clock signal when an output of the voltage controlled oscillation circuit is used as a feedback loop output, and that does not generate jitter due to unbalance or a phase difference in output amplitude between the positive and negative outputs in the case of a differential output. Further, the invention has an object to achieve a smaller, low-cost clock shaping device by decreasing the number of components without adding the output buffer driver IC. Furthermore, the invention has an object to provide an electronic instrument using a clock shaping device adapted to the foregoing objects, for example, an electronic instrument capable of achieving synchronous compensation early in the synchronization system with the use of an optical transceiver module.